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ADT7490
Table 105. REGISTER 0x88 ? PECI CONFIGURATION REGISTER 2 (POWER-ON DEFAULT = 0x00)
Bit No.
[2:0]
[3]
[4]
[5]
[7:6]
Mnemonic
RES
DOM3
DOM2
DOM1
#CPU
R/W (Note 1)
R/W
R/W
R/W
R/W
R/W
Description
Reserved
CPU domain count information. Set to 0 indicates that CPU 4 associated with the PECI3
reading has a single domain (default). Set to 1 indicates that the system CPU4 contains two
domains.
CPU domain count information. Set to 0 indicates that CPU 3 associated with the PECI2
reading has a single domain (default). Set to 1 indicates that the system CPU3 contains two
domains.
CPU domain count information. Set to 0 indicates that CPU 2 associated with the PECI1
reading has a single domain (default). Set to 1 indicates that the system CPU2 contains two
domains.
CPU count. These bits indicate the number of CPUs in the system, which provide PECI
thermal information to the ADT7490.
00 = 1 CPU (default); indicates that PECI0 data is available from CPU 1 at Address 0x30.
01 = 2 CPUs; indicates that PECI0 data is available from CPU1 at Address 0x30 and PECI1
data is available from CPU 2 at Address 0x31.
10 = 3 CPUs; indicates that PECI0 data is available from CPU1 at Address 0x30, PECI1 data
is available from CPU 2 at Address 0x31 and PECI2 data is available from CPU 3 at
Address 0x32.
11 = 4 CPUs; indicates that PECI0 data is available from CPU1 at Address 0x30, PECI1 data
is available from CPU 2 at Address 0x31, PECI2 data is available from CPU 3 at
Address 0x32 and PECI3 data is available from CPU 4 at Address 0x33.
1. This register becomes read-only when the Configuration Register 1 (0x40) Lock bit is set to 1. Any subsequent attempts to write to this
register fail.
Table 106. OPERATING POINT REGISTERS (Note 1 and 2)
Register Address
0x8A
0x8B
0x8C
0x8D
R/W (Note 3)
R/W
R/W
R/W
R/W
Description
PECI Operating Point Register
Remote 1 Operating Point Register (Default = 100 ? C)
Local Temperature Operating Point Register (Default = 100 ? C)
Remote 2 Operating Point Register (Default = 100 ? C)
Power-On Default
0xFB
0x64
0x64
0x64
1. These registers set the target operating point for each temperature channel when the dynamic T MIN control feature is enabled.
2. The fans being controlled are adjusted to maintain temperature about an operating point.
3. This register becomes read-only when the Configuration Register 1 (0x40) Lock bit is set to 1. Any subsequent attempts to write to this
register fail.
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